Electronics can be divided into a simple hierarchy consisting of devices such as integrated circuit (IC) chips, packages, printed circuit boards (PCB), and systems. The package is the interface between an IC chip and a PCB. IC dies are made from semiconductor materials such as silicon. Dies are then assembled into semiconductor packages such as quad flat packs (QFP), pin grid arrays (PGA), ball grid arrays (BGA), three dimensional integrated circuits (3DIC), wafer level packages (WLP), or package on package (PoP) devices, using wire bonding (WB), tape automated bonding (TAB), or flip chip (FC) bumping assembly techniques. The packaged die is then attached either directly to a PCB or to another substrate as the second level packaging.
3DIC technologies are known as vertical interconnect packaging technologies as they exploit the vertical dimension of the chip to reduce interconnect length and to achieve greater integration efficiency. The techniques for 3DIC package include wire-bonding, micro-bumps, through-vias, and more. A silicon interposer can be used to form a 3DIC package, where the interposer provides die-to-die interconnections for dies mounted on the interposer. For example, two dies may be bonded above each other by face-to-face or face-to-back stacking, with the lower die being coupled to the interposer by connectors such as micro-bumps. Alternatively, multiple dies may also be mounted in parallel above an interposer, and coupled to the interposer by connectors such as micro-bumps.
Semiconductor packages equipped with wireless data and communication systems comprise various RF (radio frequency) transmitting structures, which sometimes are built on chip or in-package. Electromagnetic RF waves or signals are conveyed through the packages or devices by conductive structures referred to as transmission lines. Transmission lines, as an example, may be used for interconnecting individual electrical elements together in a Monolithic Microwave Integrated Circuit (MMIC), and for interconnecting MMICs together within microwave Multi Chip Modules (MCMs).
In general, a transmission line includes at least two electric conductors or lines wherein one of the lines forms a ground (also referred to as “ground plane”) and the other forms a signal transmission line. The signal transmission line is variously arranged and combined with one or more ground planes or ground lines to form different types of conductive transmission lines such as microstrip, coplanar waveguide (CPW), grounded coplanar waveguide (GCPW) transmission lines to serve various RF signal applications. The signal transmission lines and ground conductors or planes are generally supported by some type of insulating substrate or material such as a dielectric.
As semiconductor technology continues to advance and chip package size shrinks, such as by employing 3DIC die stacking, the distance between metal layers in the conductive CMOS (complementary metal-oxide semiconductor) structure becomes smaller, leading to increasingly larger capacitance between the metal layers and reduced performance of RF devices. In addition, designing and fabricating transmission lines on-chip in a single chip or die becomes increasingly difficult with shrinking die packages in advanced semiconductor manufacturing technology nodes like the 20 nm process. Methods and apparatus are needed for designing and fabricating transmission lines with improved performance.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.